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voltage regulators 1 AN8018sa 1.8-volt 2-channel step-up, step-down, or inverting dc-dc converter control ic n overview the AN8018sa is a two-channel pwm dc-dc con- verter control ic that features low-voltage operation. this ic can obtain the step-up, step-down and invert- ing voltages with a small number of external components. the minimum operating voltage is as low as 1.8 v so that it can operate with two dry batteries. in addition, since it uses the 16-pin surface mounting type package with 0.65 mm pitch, it is suitable for miniaturized highly efficient potable power supply. n features wide operating supply voltage range (1.8 v to 14 v) incorporating a high precision reference voltage circuit (allowance: 2%) control in a wide output frequency range is possible (20 khz to 1 mhz). built-in wideband error amplifier (single gain bandwidth 10 mhz typical) built-in timer latch short-circuit protection circuit (charge current 1.1 m a typical) incorporating the under-voltage lock-out circuit (u.v.l.o.) (circuit operation-starting voltage 1.67 v typical) dead-time is variable. flatness of switching current can be obtained by staggering the turn-on timing of each channel. built-in unlatch function when dt1 pin is low level, or dt2 pin is high level, independent turn-off is possible. incorporating a on/off control function (active-high control input, standby mode current: 5 m a maximum) parallel operation is possible. output block ? totem pole 1 output ? output source-current: - 50 ma maximum ( constant current output with a less supply voltage fluctuation is possible by connecting an external resistor to pin 11) ? output sink-current: + 80 ma maximum ? open-collector 1 output ? output current: 50 ma maximum n applications lcd displays, digital still cameras, and pdas unit: mm ssop016-p-0225a 18 0.5 0.2 (1.0) 0 to 10 16 5.0 0.2 4.4 0.2 6.4 0.3 1.2 0.2 0.1 0.1 9 0.65 (0.225) 0.22 + 0.10 - 0.05 0 .1 5 + 0.10 - 0.05 seating plane
2 AN8018sa voltage regulators n block diagram n pin descriptions pin no. symbol description 1 osc pin for oscillation timing resistor and capacitor connection 2 s.c.p. pin for connecting the time constant set- ting capacitor for short-circuit protection 3in + 1 error amplifier 1 block noninverting input pin 4in - 1 error amplifier 1 block inverting input pin 5 fb1 output pin of error amplifier 1 block 6 dt1 pwm1 block dead-time setting pin 7 out1 out1 block open-collector type output pin pin no. symbol description 8 gnd grounding pin 9v cc power supply voltage application pin 10 out2 out2 block push-pull type output pin 11 rb2 out2 block output source current setting resistor connection pin 12 dt2 pwm2 block dead-time setting pin 13 fb2 output pin of error amplifier 2 block 14 in + 2 error amplifier 2 block inverting input pin 15 off on/off control pin 16 v ref reference voltage output pin out1 7 gnd 8 on/ off 15 in + 2 14 fb2 13 1.19 v h l fb1 5 in - 1 4 v ref 16 osc 1 dt1 6 v cc 9 dt2 12 s.c.p. 2 u.v.l.o. s.c.p. comp. v ref unlatch2 unlatch1 q r s latch reference voltage source v ref on/off control 1.19 v 0.9 v 0.9 v pwm1 0.9 v in + 1 3 0.22 v 0.2 v 0.9 v v ref v cc v ref rb2 11 out2 10 pwm2 triangular wave oscillation error amp. 1 error amp. 2
3 voltage regulators AN8018sa n absolute maximum ratings parameter symbol rating unit supply voltage v cc 15 v off terminal allowable application voltage v off 15 v in + 1 terminal allowable application voltage * 2 v in - 1 6v in - 1 terminal allowable application voltage * 2 v in - 1 6v in + 2 terminal allowable application voltage * 2 v in + 2 6v out1 terminal allowable application voltage v out 15 v supply current i cc ? ma out1 terminal output current i o + 50 ma out2 terminal source current i so(out) - 50 ma out2 terminal sink current i si(out) + 80 ma power dissipation * 1 p d 135 mw operating ambient temperature t opr - 30 to + 85 c storage temperature t stg - 55 to + 150 c n recommended operating range parameter symbol range unit supply voltage v cc 1.8 to 14 v off control terminal application voltage v off 0 to 14 v output source current i so(out) - 40 (minimum) ma output sink current i si(out) 70 (maximum) ma timing resistance r t 1 to 51 k w timing capacitance c t 100 to 10 000 pf oscillation frequency f out 20 to 1 000 khz short-circuit protection time constant c scp 1 000 (minimum) pf setting capacitance output current setting resistance r b 180 to 15 000 w n electrical characteristics at v cc = 2.4 v, c ref = 0.1 m f, t a = 25 c parameter symbol conditions min typ max unit reference voltage block reference voltage v ref i ref = - 0.1 ma 1.166 1.19 1.214 v input regulation with input fluctuation line v cc = 1.8 v to 14 v ? 15 30 mv load regulation load i ref = - 0.1 ma to - 1 ma - 20 - 5 ? mv note) 1. do not apply external currents or voltages to any pins not specifically mentioned. for the circuit currents, ' + ' denotes current flowing into the ic, and ' - ' denotes current flowing out of the ic. 2. except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for t a = 25 c. 3. * 1: t a = 85 c. for the independent ic without a heat sink. note that applications must observe the derating curve for the relationship between the ic power consumption and the ambient temperature. * 2: v in - 1 , v in-1 , v in + 2 = v cc when v cc < 6 v.
4 AN8018sa voltage regulators n electrical characteristics at v cc = 2.4 v, c ref = 0.1 m f, t a = 25 c (continued) parameter symbol conditions min typ max unit u.v.l.o. block circuit operation start voltage v uon 1.59 1.67 1.75 v error amplifier 1 block input offset voltage v io - 6 ?+ 6mv common-mode input voltage range v icr 0.3 ? 0.7 v input bias current 1 i b1 - 0.6 - 0.2 ?m a high-level output voltage 1 v eh1 0.83 0.93 1.03 v low-level output voltage 1 v el1 ?? 0.2 v output source current 1 i so(fb)1 - 61 - 47 - 33 m a output sink current 1 i si(fb)1 33 47 61 m a error amplifier 2 block input threshold voltage v th 1.16 1.19 1.22 v input bias current 2 i b2 ? 0.2 0.8 m a high-level output voltage 2 v eh2 0.83 0.93 1.03 v low-level output voltage 2 v el2 ?? 0.2 v output source current 2 i so(fb)2 - 61 - 47 - 33 m a output sink current 2 i si(fb)2 33 47 61 m a oscillator block output off threshold voltage v th(osc) 0.8 0.9 1.0 v output 1 block oscillation frequency 1 f out1 r t = 12 k w , c t = 330 pf 185 205 225 khz output duty ratio 1 du 1 75 80 85 % output saturation voltage v o(sat) i o = 30 ma ?? 0.5 v output leak current i ole v cc = 14 v ?? 1 m a output 2 block oscillation frequency 2 f out2 r t = 12 k w , c t = 330 pf 185 205 225 khz output duty ratio 2 du 2 72 77 82 % high-level output voltage v oh i o = - 10 ma, r b = 820 w 1.4 ?? v low-level output voltage v ol i o = 10 ma, r b = 820 w?? 0.2 v output source current i so(out) v o = 0.7 v, r b = 820 w- 40 - 30 - 20 ma output sink current i si(out) v o = 0.7 v, r b = 820 w 20 ?? ma pull-down resistance r o 20 30 40 k w pwm1 block output full-off input threshold v t0-1 duty = 0% ? 0.28 0.30 v voltage 1 output full-on input threshold v t100-1 duty = 100% 0.65 0.72 ? v voltage 1 input current 1 i dt1 v dt1 = 0.4 v - 1.1 - 0.5 ?m a
5 voltage regulators AN8018sa n electrical characteristics at v cc = 2.4 v, c ref = 0.1 m f, t a = 25 c (continued) parameter symbol conditions min typ max unit pwm2 block output full-off input threshold v t0-2 duty = 0% 0.65 0.72 ? v voltage 2 output full-on input threshold v t100-2 duty = 100% ? 0.28 0.30 v voltage 2 input current 2 i dt2 v dt2 = 0 v - 1.1 - 0.5 ?m a unlatch circuit 1 block input threshold voltage 1 v thul1 0.15 0.20 0.25 v unlatch circuit 2 block input threshold voltage 2 v thul2 0.8 0.9 1.0 v short-circuit protection circuit block input standby voltage v stby ? 60 120 mv input threshold voltage 1 v thpc1 0.8 0.9 1.0 v input threshold voltage 2 v thpc2 0.17 0.22 0.27 v input latch voltage v in ? 60 120 mv charge current i chg v scp = 0 v - 1.43 - 1.1 - 0.77 m a on/off control block input threshold voltage v on(th) 0.8 1.0 1.3 v whole device output off consumption current i cc(off) r b = 820 w, duty = 0% ? 5.7 8.0 ma latch mode consumption current i cc(la) r b = 820 w? 5.6 7.8 ma standby current i cc(sb) ?? 1 m a design reference data note) the characteristics listed below are theoretical values based on the ic design and are not guaranteed. parameter symbol conditions min typ max unit reference voltage block v ref temperature characteristics v refdt t a = - 30 c to + 85 c - 1 ?+ 1% over-current protection drive current i oc ?- 11 ? ma u.v.l.o. block reset voltage v r ? 0.8 ? v error amplifier 1/2 blocks v th temperature characteristics v thdt t a = - 30 c to + 85 c - 0.3 ?+ 0.3 mv/ c open-loop gain a v ? 57 ? db single gain bandwidth f bw ? 10 ? mhz output 1/2 blocks frequency supply voltage f dv - 1 ?+ 1% characteristics frequency temperature characteristics f dt - 3 ?+ 3%
6 AN8018sa voltage regulators pin no. equivalent circuit description i/o 1 osc: o the terminal used for connecting a timing capaci- tor/resistor to set oscillation frequency. use a capacitance value within the range of 100 pf to 10 000 pf and a resistance value within the range of 3 k w to 30 k w . use an oscillation frequency in the range of 20 khz to 1 mhz. when operating the circuit in parallel and synchronously, the channel 2 output stops when this pin becomes 0.9 v or more. (refer to the "application notes, [7]" section.) 2 s.c.p.: o the terminal for connecting a capacitor to set the time constant of the timer latch short-circuit pro- tection circuit. use a capacitance value in the range of 1 000 pf or more. the charge current i chg is 1.1 m a typical. 3in + 1: i the noninverting input pin for error amplifier 1 block. 4in - 1: i the inverting input pin for error amplifier 1 block. 5 fb1: o the output pin for error amplifier 1 block. the source current is - 47 m a and the sink current is 47 m a. correct the frequency characteristics of the gain and the phase by connecting a resistor and a capa- citor between this terminal and gnd. n terminal equivalent circuits q s latch 0.2 v r v cc 1 q s 1.19 v r 1.1 m a v cc 2 2 k w latch output cut-off v cc 100 w 100 w 4 3 in + 1 5 in - 1 47 m a osc pwm 47 m a n electrical characteristics at v cc = 2.4 v, c ref = 0.1 m f, t a = 25 c (continued) design reference data (continued) note) the characteristics listed below are theoretical values based on the ic design and are not guaranteed. parameter symbol conditions min typ max unit output 2 block rb terminal voltage v b ? 0.36 ? v short-circuit protection block comparator threshold voltage v thl ? 1.19 ? v on/off control block off terminal current i off ? 23 ?m a
7 voltage regulators AN8018sa pin no. equivalent circuit description i/o 6 dt1: i the pin for setting channel 1 output maximum duty ratio. if this terminal is set at a voltage of 0.20 v or less, fb1 terminal becomes low-level voltage and the protective function for channel 1 output short- circuit will stop (unlatch function). 7 out1: o the pin is open-collector type output terminal. the absolute maximum rating of output current is + 50 ma. 8 gnd: ? grounding terminal 9v cc : ? the supply voltage application terminal use the operating supply voltage in the range of 1.8 v to 14 v. 10 out2: o the pin is push-pull type output terminal. the absolute maximum rating of output source current is - 50 ma. the absolute maximum rating of output sink cur- rent is + 80 ma. a constant current output with less fluctuation with power supply voltage and dispersion can be obtained by the resistor externally attached to rb2 pin. i so(out)2 = 68 v rb2 [a] r b2 11 rb2: i the pin for connecting a resistor for setting chan- nel 2 output current. use a resistance value in the range of 180 w to 1.1 k w . the terminal voltage is 0.36 v (at r b2 = 820 w ). v cc 7 8 9 v cc i so(out) 10 30 k w rb2 v cc 11 120 w out2 n terminal equivalent circuits (continued) v cc fb1 6 0.2 v osc pwm
8 AN8018sa voltage regulators pin no. equivalent circuit description i/o 12 dt2: i the pin for setting channel 2 output maximum duty ratio. if this terminal is set at a voltage of 0.9 v or more, fb2 terminal becomes high-level voltage and the protective function for channel 2 output short- circuit will stop (unlatch function). 13 fb2: o the output pin for error amplifier 2 block. the source current is - 47 m a and the sink current is 47 m a. correct the frequency characteristics of the gain and the phase by connecting a resistor and a ca- pacitor between this terminal and gnd. 14 in + 2: i the noninverting input pin for error amplifier 2 block. 15 off: i the terminal for on/off control. high-level input: normal operation (v off > 1.3 v) low-level input: standby state (v off < 0.8 v) the total current consumption in the standby state can be suppressed to a value 1 ma or less. 16 v ref :o the output terminal for the internal reference voltage. the reference voltage is 1.19 v (allowance: 2%) at v cc = 2.4 v and i ref = - 0.1 ma. connect a capacitor of 0.01 m f or more between v ref and gnd for phase compensation. v cc in + 2 13 1.19 v 47 m a osc pwm 47 m a 100 w v cc 1.19 v 14 30 k w internal circuit start/stop 60 k w 15 v cc 16 n terminal equivalent circuits (continued) v cc fb2 12 0.9 v osc pwm 0.9 v
9 voltage regulators AN8018sa n usage notes [1] the loss p of this ic increases in proportion to the supply voltage. use the ic so as not to exceed the allowable power dissipation of package p d . reference formula: p = v o(sat)1 i out1 du 1 + (v cc - v beq2 ) i so(out) du 2 + v cc i cc < p d v o(sat)1 : out1 terminal saturation voltage (0.5 v maximum at i out1 = 30 ma) i out1 : out1 terminal output current ( = {v cc - v beq1 - v o(sat)1 } / r o1 ) du 1 : output1 duty ratio v beq2 : base-emitter voltage of npn transistor q2 i so(out) : out2 terminal output source current (set by rb, i so(out) = 40 ma maximum at rb2 = 820 w ) du 2 : output2 duty ratio i cc :v cc terminal current (8.0 ma maximum but at v cc = 2.4 v) [2] since the output 2 of the AN8018sa is assuming the bipolar transistor driving, it is necessary to pay attention to the following points when directly driving n-channel mosfet. 1. select an n-channel mosfet having a low input capacitance the AN8018sa is of the constant-current (50 ma maximum) output source-current type circuit assum- ing the bipolar transistor driving. also, its sink cur- rent capability is around 80 ma maximum. for those reason, it is necessary to pay attention to the increase of loss due to the extension of the output rise time and the output fall time. if any problem arises, there is a method to solve it by amplifying with inverters as shown in figure 1. 2. select an n-channel mosfet having a low gate threshold value the output high-level voltage of out2 pin of the AN8018sa is v cc - 1.0 v minimum, so that it is necessary to select a low v t mosfet having a suffi- ciently low on-state resistance in accordance with the using operating supply voltage. if a larger v gs is desired, there is a method to apply the double-voltage of the input to the ic's v cc pin by using the transformer as shown in figure 2. [3] in order to realize a low noise and high efficiency, a care should be taken in the following points in designing the board layout. 1. the wiring for ground line should be taken as wide as possible and grounded separately from the power system. 2. the input filter capacitor should be arranged in a place as close to v cc and gnd pin as possible so as not to allow switching noise to enter into the ic inside. 3. the wiring between the out terminal and switching device (transistor or mosfet) should be as short as possible to obtain a clean switching waveform. 4. in wiring the detection resistor of the output voltage, the wiring for the low impedance side should be longer. [4] there is a case in which this ic does not start charging to the s.c.p. capacitor when the output is short-circuited due to the malfunction of u.v.l.o. circuit biased by v cc that has ripples generated by turning on and off of the switching transistor. the allowable range of the v cc ripple is as shown in the following figure. reduce the v cc ripple by inserting a capacitor near the v cc terminal and gnd terminal of this ic so that the v cc ripple is in this allowable range. however, this allowable range is design reference value and not the guaranteed value. sbd v in figure 1. output boost circuit example figure 2. gate drive voltage increasing method out2 out2 v out sbd v in v cc ? 2 v in - v d v cc v out sbd 9 10 10
10 AN8018sa voltage regulators 700 582 100 135 200 233 300 400 338 500 600 0 0 25 85 125 50 75 100 independent ic without a heat sink r th( j - a) = 295.6 c/w glass epoxy board (50 50 t0.8 mm 3 ) r th(j - a) = 171.8 c/w ambient temperature t a ( c) power dissipation p d (mw) n usage notes (continued) [4] (continued) v cc ripple allowable range v cc ripple frequency (mhz) 0.1 100 1.5 1 0.3 0.5 0 v cc ripple width (v[p-p]) 0.5 1 2 10 recommended operating range n application notes [1] p d ? t a curves of ssop016-p-0225a p d ? t a 1.185 1.195 - 30 t a ( c) v ref (v) 1.190 - 10 10 30 50 70 90 10k 1m 1k 10k 100k r t ( w ) f out (hz) 100k c t = 100 pf c t = 330 pf c t = 0.01 m f [2] main characteristics v ref temperature characteristics frequency characteristics
11 voltage regulators AN8018sa 0 8 0 v cc (v) i cc(off) (ma) 2 4 6 8 10 12 14 1 2 3 4 5 6 7 0 12 100 1k 10k r b ( w ) i cc(off) (ma) 2 4 6 8 10 0 90 100k 10k 1k 100 r b ( w ) i si(out) (ma) 10 20 30 40 50 60 70 80 v cc = 1.8 v v cc = 2.4 v v cc = 14 v v cc = 7 v 0 70 100k 10k 1k 100 r b ( w ) i so(out) (ma) 10 20 30 40 50 60 v cc = 1.8 v v cc = 2.4 v v cc = 14 v v cc = 7 v du 1 ? v dt1 du 2 ? v dt2 i cc(off) ? v cc i cc(off) ? r b n application notes (continued) [2] main characteristics i so(out) ? r b i si(out) ? r b 0 100 0.2 v dt1 (v) du 1 (%) 10 20 30 40 50 60 70 80 90 0.3 0.4 0.5 0.6 0.7 0.8 0 100 0.2 v dt2 (v) du 2 (%) 10 20 30 40 50 60 70 80 90 0.3 0.4 0.5 0.6 0.7 0.8
12 AN8018sa voltage regulators n application notes (continued) [3] timing chart (inside waveform) fb1 osc dt1 dt2 osc fb2 channel 1 1.6 v 1.22 v v cc terminal voltage waveform s.c.p. terminal voltage waveform out1 terminal voltage waveform open-collector output out 2 terminal voltage waveform totem pole output channel 2 output short-circuit
13 voltage regulators AN8018sa n application notes (continued) [4] function descriptions 1. reference voltage block this block is composed of the band gap circuit, and outputs the temperature compensated 1.19 v reference voltage. the reference voltage is stabilized when the supply voltage is 1.8 v or more. the reference voltage is also used as the reference voltage for the error amplifier 2 block. 2. triangular wave oscillation block the sawtooth-waveform-like triangular wave having a peak of approximately 0.7 v and a trough of approxi- mately 0.2 v can be generated by connecting the timing capacitor c t and resistor r t to the osc terminal (pin 1). the oscillation frequency can be freely set by the value of c t and r t to be connected externally. the usable oscilla- tion frequency is from 20 khz to the maximum 1 mhz. the triangular wave is connected with the inverting input of pwm comparator for channel 1 side and the noninverting input of pwm comparator for channel 2 side within the ic inside. rough calculation of oscillation fre- quency can be calculated by the following equation. f osc ? - 1 ? 0.8 1 [hz] c t r t ln v oscl c t r t v osch however, boosting charge time, over-shoot and under shoot quantities are not considered in the above equation. and refer to the experimentally determined graph of the frequency characteristics provided in the main characteristics section. 3. error amplifier 1 block the output voltage of dc-dc converter is detected by the pnp-transistor-input type error-amplifier and the amplified signal is input to the pwm comparator. also, it is possible to perform the gain setting and the phase compensation arbitrarily by connecting a resistor and a capacitor from the fb1 terminal (pin 5) to gnd in series. the output voltage v out1 can be set by making connection as shown in figure 2. t 1 t 2 t v osch ? 0.7 v v oscl ? 0.2 v figure 1. triangular wave oscillation waveform boosting charge discharging fb2 r1 r2 5 to pwm comparator input error amplifier 1 block in + 13 in - 14 v ref v out1 = v ref figure 2. connection method of error amplifier 1 block case of step-up output r3 + r4 r4 r3 r4 v out1 r2 r1 + r2 fb2 r1 r2 5 to pwm comparator input error amplifier 1 block in + 13 in - 14 v ref v out1 v out1 = - (v ref - v in - 1 ) + v ref case of inverting output r1 + r2 r1 r3 r4 v in - 1 = v ref r4 r3 + r4 4. error amplifier 2 block the output voltage of dc-dc converter is detected by the npn-transistor-input type error-amplifier and the amplified signal is input to the pwm comparator. the internal reference voltage 1.19 v is given to the noninverting input.
14 AN8018sa voltage regulators n application notes (continued) [4] function descriptions (continued) 4. error amplifier 2 block (continued) also, it is possible to perform the gain setting and the phase compensation arbitrarily by con- necting a resistor and a capacitor from the fb2 terminal (pin 13) to gnd in series. the output voltage v out2 can be set by mak- ing connection as shown in figure 3. 5. timer latch short-circuit protection circuit this circuit protects the external main switching devices, flywheel diodes, and choke coils, etc. from destruction or deterioration if overload or short-circuit condition of power supply output lasts for a certain time. the timer latch short-circuit protection circuit detects the output level of the error amplifier. when the output voltage of dc-dc converter drops and the fb1 terminal (pin 5) becomes 0.9 v or more, or the fb2 terminal (pin 13) becomes 0.22 v or less, the low-level output is given and the timer circuit is actuated to start the charge of the external protection-enable capacitor. if the output of the error amplifier does not return to a normal voltage range by the time when the voltage of this capacitor reaches 1.19 v, it sets the latch circuit, and cuts off the output drive transistor, and sets the dead-time to 100%. 6. low input voltage malfunction prevention circuit (u.v.l.o.) this circuit protects the system from destruction or deterioration due to control malfunction when the supply voltage is low in the transient state of power on/off. the low input voltage malfunction prevention circuit detects the internal reference voltage which changes according to the supply voltage level. until the supply voltage reaches 1.67 v during its rise time, it cuts off the output drive transistor, and sets the dead-time to 100%. at the same time, it holds the s.c.p. terminal (pin 2) and dt1 terminal (pin 6) to low-level, and the osc terminal (pin 1) and dt2 terminal (pin 12) to high-level. 7. pwm comparator block the pwm comparator controls the on-period of the output pulse according to the input voltage. the pwm1 and pwm2 block are set in an opposite logic relation of each other and on-period of each output is staggered. the pwm1 block turns on the output transistor during the period when the triangular wave of osc terminal (pin 1) is lower than any lower one of the fb1 (pin 5) terminal voltage and the dt1 (pin 6) terminal voltage. the pwm2 block turns on the output transistor during the period when the triangular wave of osc terminal (pin 1) is higher than any higher one of the fb2 (pin 13) terminal voltage and the dt2 (pin 12) terminal voltage. the maximum duty ratio is variable from the outside. also, the soft start which gradually extends on-period of the output pulse is activated by connecting a capaci- tor in parallel with the resistor-dividing for the maximum duty ratio setting. 8. unlatch block the unlatch circuit 1 block fixes the fb1 terminal (pin 5) at low level at the dt1 terminal (pin 6) is 0.20 v or less. the unlatch circuit 2 block fixes the fb2 terminal (pin 13) at high-level at the dt2 terminal (pin 12) is 0.9 v or more. consequently, by controlling the dt1 and the dt2 terminal voltages, it is possible to operate only one channel or to start and stop each channel in any required sequence. 9. output 1 block this output circuit is open-collector type. the available output current is up to 50 ma. the breakdown voltage of output terminal is 15 v. 10. output 2 block this block uses a totem pole type output circuit. by connecting the current setting resistor to the rb2 terminal, it is possible to arbitrarily set a constant-current source-output having a small fluctuation with the supply voltage. the available constant-current source-output is up to 50 ma. fb2 r1 r2 13 1.19 v to pwm comparator input error amplifier 2 block in + 2 14 v out2 v out2 = 1.19 r 1 + r 2 r 2 figure 3. connection method of error amplifier 2 block (step-up output)
15 voltage regulators AN8018sa n application notes (continued) [5] about logic of pwm block the logic for channel 1 and channel 2 of this ic is reversed. thereby an input current flatness is realized. at the same time, noise can be suppressed to a lower level by staggering the turn on timing. the pwm1 block turns on the output transistor during the period when the triangular wave of the osc terminal (pin 1) is lower than both of the fb1 (pin 5) terminal voltage and the dt1 (pin 6) terminal voltage. the pwm2 block turns on the output transistor during the period when the triangular wave of osc terminal (pin 1) is higher than both of the fb2 (pin 13) terminal voltage and the dt2 (pin 12) terminal voltage. (refer to figure 4.) fb1 osc fb2 channel 1 switching transistor emitter current i e1 channel 2 switching transistor collector current i c2 i e1 + i c2 out1 (open-collector output) out2 (totem pole output) v in i c2 sbd + i e1 sbd - out2 10 out1 7 figure 4. pwm logic explanation chart dt1 and dt2 are omitted
16 AN8018sa voltage regulators n application notes (continued) [6] time constant setting method for timer latch short-circuit protection circuit the constructional block diagram of protection latch circuit is shown in figure 6. the comparator for short-circuit protection compares the error amplifier 1 output fb1 with the reference voltage of 0.9 v for channel 1 side, and the error amplifier 2 output fb2 with the reference voltage of 0.22 v for channel 2 side at all the time. when the load conditions of dc-dc converter output is stabilized, there is no fluctuation of error amplifier output and the short-circuit protection comparator also keeps the balance. at this moment, the output transistor q1 is in the conductive state and the s.c.p. terminal is held to approximately 60 mv. when the load conditions for channel 1 side suddenly change and high-level signal (0.9 v or more) is input from the error amplifier 1 block to the short-circuit protection comparator, the short-circuit protection comparator outputs the low-level signal to cut off the output transistor q1. also, when the load conditions for channel 2 side suddenly change and low-level signal (0.22 v or less) is inputted from the error amplifier 2 block to the short-circuit protection comparator, the short-circuit protection comparator outputs the low-level signal to cut off the output transistor q1. the capacitor c scp connected to the s.c.p. terminal starts charging. when the external capacitor c scp has been charged to approximately 1.19 v with the constant current of approximately 1.1 m a, the latch circuit is set, the output terminal is fixed to low level, and the dead-time is set to 100%. once the latch circuit is set, the s.c.p. terminal is discharged to approximately 40 mv, however, the latch circuit is not reset unless the power for the latch circuit is turned off or restarted by the on/off control. 1.19 v = i chg t pe c scp \ t pe [s] = 1.08 c scp when the power supply is turned on, the output is considered to be short-circuited state so that the s.c.p. terminal voltage starts charging. it is necessary to set the external capacitor so as to start up the dc-dc converter output voltage before setting the latch circuit in the later stage. especially, pay attention to the delay of the start-up time when applying the soft-start. figure 5. s.c.p. terminal charging waveform v scp [v] t [s] short-circuit detection time t pe 0.06 1.19 fb2 13 1.19 v q1 error amp.2 s.c.p. comp. in + 214 s.c.p. 2 0.22 v high-level detection comp. 1.19 v fb1 5 3 error amp.1 in + 1 4 in - 1 0.9 v 1.1 m a u.v.l.o. q r s on/off control figure 6. short-circuit protection circuit internal reference latch output cut-off
17 voltage regulators AN8018sa 0.1 m f l h 1 2 3 4 5 6 7 8 dt1 in + 1 in - 1 s.c.p. v cc gnd out1 1 2 3 4 5 6 7 8 out2 fb1 fb2 rb2 in + 2 dt2 osc dt1 in + 1 in - 1 s.c.p. gnd out1 fb1 off v cc out2 fb2 rb2 in + 2 dt2 v ref v ref osc off 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 figure 7. slave operation circuit example input off terminals connected together osc terminals connected together n application notes (continued) [7] parallel synchronous operation of multiple ics multiple instances of this ic can be operated in parallel. if the osc terminals (pin 1) and off terminals (pin 15) are connected to each other as shown in figure 7, the ics will operate at the same frequency. it is possible to operate this ic (the AN8018sa) with the two-channel totem pole output ic an8017sa in parallel synchronous mode. 1. usage notes 1) the parallel synchronous operation with the single-channel an8016sh/an8016nsh is not possible. 2) the remote on/off with the single ic itself is not possible. only the simultaneous remote on/off of all ics is possible.
18 AN8018sa voltage regulators n application notes (continued) [7] parallel synchronous operation of multiple ics (continued) 2. about the operation of short-circuit protection at parallel synchronous operation in the case of the operation in parallel, if the single output (or multiple outputs) of them is short-circuited and the timer latch short circuit protection of the ic is operated, the output of other ics will be also shut down, then enter into latch mode. in figure 8, if the ic-2 entered timer latch mode, q1 turns on and the osc terminal (pin 1) is fixed to approximately 1.1 v and the oscillator stops. then channel 1 of ic-1 becomes low level than the dt1 terminal (pin 6) voltage or high-level voltage (0.9 v) of the fb1 terminal set by terminal voltage, and then output 2 stops by pwm1 circuit of inside. the channel 2 stops output 2 by oscillator high-level detection comparator. and then, the ic-1 becomes short-circuit state and enters latch mode after a certain time. it becomes the same operation in case of the ic-1 enters latch mode previously. s.c.p. ic-2 side output short-circuited 1.19 v dt1 fb1 out1 osc since the osc terminal voltage becomes higher than the dt1 terminal voltage, the out1 becomes fully off state. fb2 dt2 out2 osc s.c.p. 1.19 v oscillator high-level detection comparator v osc = v ref - v ce(sat) = becomes approximately 1.1 v forced to be in off state inside the ic ic-1 latch ic-2 latch 16 0.9 v ic-1 1 16 ic-2 q1 1 channel 2 goes off at high the ic entering to the lach mode, q1 turns on and, figure 8. operation of short-circuit protection at parallel synchronous operation
19 voltage regulators AN8018sa n application notes (continued) [8] setting of off-terminal connection resistor the start circuit starts its operation when q1 is turned on. in case of the resistor r off is connected externally as shown in figure 9, the input voltage v ctl at which the start circuit operates is obtained by the equation: v ctl > v beq1 (r off + r 1 + r 2 ) / r 2 therefore, r off can be set by: r off < r 2 v ctl / v beq1 - r 1 - r 2 set the value of r off according to above equations. (typical value) r off < 25 k w including temperature characteristics and sample to sample variations at v ctl = 3 v. [9] sequential operation in the case of sequential operation is necessary for each channel at ic operation, it is possible to turn on/off the output of dc-dc converter individually by turning on/off q1 and q2 as shown in figure 10. in the channel 1 side, if q1 turns on and the dt1 terminal (pin 6) becomes 0.2 v or less, the output transistor turns off due to lower voltage than the osc terminal (pin 1). simultaneously, unlatch circuit 1 block operates, and the timer latch short-circuit protection does not operate because the fb1 terminal (pin 5) becomes fixed to low even if output of channel 1 downs. in the channel 2 side, if q1 turns on and the dt2 terminal (pin 12) becomes 0.9 v or more, the output transistor turns off due to higher voltage than the osc terminal (pin 1). simultaneously, unlatch circuit 2 block operates, and the timer latch short-circuit protection does not operate because the fb2 terminal (pin 13) becomes fixed to high even if output of channel 2 downs. r off ctl off 15 r1 30 k w r2 60 k w q1 figure 9. off terminal peripheral circuit start circuit v 1 v 2 0.9 v 0.9 v unlatch2 q1 q2 1.19 v 5 6 7 8 fb1 v cc gnd out1 16 13 12 11 10 9 out2 dt1 fb2 rb2 dt2 v ref 0.2 v unlatch1 control block figure 10
20 AN8018sa voltage regulators n application notes (continued) [9] about sequential operation (continued) v 1 v 2 dt1 out1 dt2 out2 out1 operation out2 operation operation when each channel single on/off [10] error amplifier phase-compensation setting method the equivalent circuit of error amplifier is as shown in figure 11. the transfer function is: h = 1 / {s (c e1 + c o1 )} = 1 r e1 + 1 / {s (c e1 + c o1 )} sc o1 r e1 + 1 (from c e1 << c o1 ) the cut-off frequency is variable by changing the externally attached phase compensation capacitor c o1 . adjust by inserting a resistor r o1 between the fb1 terminal and c o1 in series as shown in figure 12 when it is required to have a gain on the high frequency side or desired to lead a phase. the transfer function is: h = sc o1 r o1 + 1 sc o1 (r o1 + r e1 ) + 1 (from c e1 << c o1 ) to pwm 1.19 v c o1 57db in - 1 c e1 5 pf figure 11. error amplifier equivalent circuit fb1 r e1 1 m w to pwm 1.19 v c o1 r o1 57db in - 1 c e1 5 pf figure 12. error amplifier equivalent circuit (r o1 inserted) fb1 r e1 1 m w
21 voltage regulators AN8018sa n ac analysis result simulation circuit 1.19 v ac c o1 r o1 fb1 in - 1 f ? v ph f ? v ph 0 20 180 1 10 100m f ( hz) v ph ( ) 40 60 80 100 120 140 160 100 1k 10k 100k 1m 10m c o1 = 0.01 m f 10 w 1 w r o1 = 10 k w 1 k w 100 w 0 20 180 1 10 100m f ( hz) v ph ( ) 40 60 80 100 120 140 160 100 1k 10k 100k 1m 10m c o1 = 1 000 pf 1 w 1 k w 100 w 10 w r o1 = 10 k w f ? v bd f ? v bd - 80 - 60 60 1 10 100m f ( hz) v db (db) - 40 - 20 0 20 40 100 1k 10k 100k 1m 10m c o1 = 0.01 m f 10 w 1 w r o1 = 10 k w 100 w 1 k w - 80 - 60 60 1 10 100m f ( hz) v bd (db) - 40 - 20 0 20 40 100 1k 10k 100k 1m 10m c o1 = 1 000 pf 10 w 1 w r o1 = 10 k w 100 w 1 k w
22 AN8018sa voltage regulators 0 20 180 1 10 100m f ( hz) phase ( ) 40 60 80 100 120 140 160 100 1k 10k 100k 1m 10m r o1 = 0 c o1 = 1 m f 0.1 m f 0.01 m f 0.001 m f 0 20 180 1 10 100m f ( hz) phase ( ) 40 60 80 100 120 140 160 100 1k 10k 100k 1m 10m c o1 = 0.1 m f r o1 = 10 k w 1 k w 100 w 10 w 1 w n ac analysis result (continued) f ? phase f ? phase f ? gain f ? gain - 80 - 60 60 1 10 100m f ( hz) gain (db) - 40 - 20 0 20 40 100 1k 10k 100k 1m 10m r o1 = 0 c o1 = 1 m f 0.1 m f 0.001 m f 0.01 m f - 80 - 60 60 1 10 100m f ( hz) gain (db) - 40 - 20 0 20 40 100 1k 10k 100k 1m 10m c o1 = 0.1 m f 1 k w 100 w 10 w 1 w r o1 = 10 k w
23 voltage regulators AN8018sa n application circuit examples circuit construction for evaluation board evaluation board vo2 sbd2 gnd l2 q2 q3 l1 sbd1 c5 vo1 c4 r5 r3 r2 r4 r8r7 r6 r1 c3 c2 c1 q1 vin r11 r13 r14 r16 r17 r18 r12 r10 c11 c10 c6 r9 c12 c9 c8 r15 on sw1 off c7 AN8018sa input + - ctl c7 c8 c9 c12 c11 c10 c6 c4 r8 r4 r5 r3 r2 r7 AN8018sa r6 c3 c2 r1 c1 r13 r11 r17 r18 r14 r15 q3 l2 l1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dt1 in + 1 in - 1 s.c.p. osc off v cc gnd out1 out2 fb1 fb2 rb2 in + 2 dt2 v ref sbd v out2 v out1 i out1 r12 - + q1 sbd i so(out)
24 AN8018sa voltage regulators 0.01 m f to 0.1 m f sw 0.1 m f 0.01 m f 0.01 m f 0.01 m f 10 m f 10 m f ma3x720 (ma720*) ma3x720 (ma720*) 2sd0602 (2sd602*) AN8018sa 100 m h 200 m h 0.1 m f 0.1 m f 12 k w 68 k w 1 k w 1 k w 68 k w 6.2 k w 82 k w 68 k w 1 k w 200 w 51 k w 51 k w 510 w 150 k w 13 k w gnd gnd 22 k w input 5 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dt1 in + 1 in - 1 s.c.p. osc off v cc gnd out1 out2 fb1 fb2 rb2 in + 2 dt2 v ref output 2 + 15 v, 50 ma output 1 - 8 v, 10 ma 330 pf 10 m f n application circuit examples (continued) application circuit example 1 (input 5 v, output 15 v/ - 8 v) note) * : former part number application circuit example 2 (input 2.5 v to 6.5 v, output 5 v/12 v) 0.01 m f to 0.1 m f 0.01 m f 0.01 m f 0.01 m f 200 m f 100 m f 10 m h 10 m h 0.1 m f 0.1 m f 10 m f 0.1 m f h l 12 k w 68 k w 1 k w 1 k w 68 k w 82 k w 9.1 k w 50 k w 39 k w 68 k w 1 k w 560 w 750 w 110 k w 12 w 51 k w 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dt1 in + 1 in - 1 s.c.p. osc off v cc gnd out1 out2 fb1 fb2 rb2 in + 2 dt2 v ref output 2 + 12 v output 1 + 5 v 330 pf input AN8018sa
25 voltage regulators AN8018sa n application circuit examples (continued) application circuit example 3 (input 12 v, output 5 v/15 v) 0.1 m f 1.19 v(typ.) 0.01 m f 0.01 m f 0.01 m f 10 m f f ? 200 khz ma3x720 (ma720*) ma3x720 (ma720*) 100 m h q1 10 m h 0.1 m f 0.1 m f 10 m f 0.1 m f 2sd0602 (2sd602*) 2sa1022 12 k w 68 k w 1 k w 1 k w 68 k w 50 k w 39 k w r3 r4 68 k w 10 k w 560 w 750 w 82 k w 9.1 k w 150 k w 13 k w 22 k w input 12 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dt1 in + 1 in - 1 s.c.p. osc off v cc gnd out1 out2 fb1 fb2 rb2 in + 2 dt2 v ref v out2 + 15 v v out1 + 5 v (0.1 a to 0.3 a) - 330 pf sw ctl AN8018sa note) * : former part number
26 AN8018sa voltage regulators n application circuit examples (continued) application circuit example 4 (circuit using the an8017sa/AN8018sa) input 1.8 v to 3.2 v remote on/off control pin - 10 v, 5 v, 18 v stop with high-level input. input voltage range: 1.8 v to 3.2 v oscillation frequency: 450 khz 0.1 m f 0.1 m f 10 m f 10 m f 10 m f 0.1 m f 0.1 m f 1.19 v 330 pf 68 k w 5.1 k w 10 k w 0.1 m f 10 k w 75 k w 300 w 68 k w 22 k w 2sd0874 (2sd874*) 2sb1440 AN8018sa 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dt1 39 k w 5 v (stby) 300 ma (max.) - 10 v 10 ma (max.) 12 k w 10 m h in + 1 s.c.p. osc off v cc gnd out1 out2 fb1 in - 1 fb2 rb2 820 w in + 2 dt2 v ref ma2q738 (ma738*) ma2q738 (ma738*) ma2q738 (ma738 *) ma2q738 (ma738*) 75 k w 47 k w 22 k w 1.5 k w 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1.19 v 68 k w 820 w 10 k w 0.1 m f 10 k w 68 k w 56 k w 22 k w 2sd0602 (2sd602 * ) 2sd0602 (2sd602 * ) an8017sa 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 rb1 51 k w 5 v 140 ma (max.) 18 v 35 ma (max.) 15 k w 10 m h 68 m h in - 1 s.c.p. osc off v cc gnd out1 out2 dt1 fb1 fb2 rb2 820 w in + 2 dt2 v ref 10 m f 56 k w 3.9 k w 18 m h note) * : former part number

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